U2753B-C preliminary information telefunken semiconductors rev. a1, 30-sep-96 1 (10) pll for dab tuner description the U2753B-Cfs is a monolithically integrated pll circuit fabricated in temic's advanced uhf5s technology. designed for applications in dab receivers it controls a vco to synthesize frequencies in the range of 70 mhz to 500 mhz in a 16 khz raster; four different reference divide factors can be selected. the lock status of the phase detector is indicated at a special output pin, six switching outputs can be addressed. an internal frequency doubler provides an output signal having twice the frequency of the reference oscillator. all functions of this ic are controlled by an i 2 c bus. features microprocessor controlled via i 2 c bus 4 addresses selectable four reference divider factors selectable: 1024, 1120, 1152, 1536 programmable 15-bit counter 1:2048 to 1:32767 three state phase detector with programmable charge pump deactivation of tuning output programmable 6 switching outputs (open collector) reference frequency doubler (open collector output) lock status indication (open collector) package: sso20 block diagram three state detector swg reference divider prog. lock detector 15 bit latch 4 bit latch gnd vs 19 20 11 12 13 14 15 swc swd swe swf adr scl 67 sda 8 4 nref 5 18 17 rf nrf plck pd vd 3 1 2 i 2 c bus interface / control mux mux ref 2 bit latch 9 swh 16 frequency doubler x 2 fdo 10 nfdo switches 7 bit latch charge pump 9612014 2 bit latch main divider phase figure 1.
U2753B-C telefunken semiconductors rev. a1, 30-sep-96 preliminary information 2 (10) ordering and package information extended type number package remarks U2753B-Cfs sso20 U2753B-Cfsg3 sso20 taping according to ice-286-3 pin description 1 2 3 4 5 6 7 8 10 9 19 18 17 16 14 15 13 12 11 20 ref nref adr scl sda nfdo vd plck nrf swh swg swf swe swd gnd rf fdo swc pd vs figure 2. pinning pin symbol function 1 pd three-state charge pump output 2 vd active filter output 3 plck lock indicating output (open collector) 4 ref reference input 5 nref reference input (inverted) 6 adr address selection 7 scl clock (i 2 c) 8 sda data (i 2 c) 9 nfdo frequency doubler output (inverted, open collector) 10 fdo frequency doubler output (open collector) 11 swc switching output (open collector) 12 swd switching output (open collector) 13 swe switching output (open collector) 14 swf switching output (open collector) 15 swg switching output (open collector) 16 swh switching output (open collector) 17 nrf rf input (inverted) 18 rf rf input 19 gnd ground 20 vs supply voltage functional description the U2753B-C is a low power frequency synthesizer designed for applications in a dab receiver. its rf operation range reaches from 70 mhz up to 500 mhz. the device includes input buffers for reference and rf dividers, a reference divider, a programmable rf divider, a tri-state phase detector, a programmable charge pump, six switching outputs, a frequency doubler for the reference input signal and a control unit. the control unit has to be accessed by a micro controller via an i 2 c bus. the programming information is stored in a set of internal registers. a block diagram of this circuit is shown in figure 1. its pinning can be taken from figure 2. in figure 5 a typical application circuit is given. reference divider four different scaling factors of the reference divider can be selected by means of the bits `rd1' and `rd2' in the i 2 c bus instruction code: 1024, 1120, 1152 and 1536. starting form a reference oscillator frequency of 16.38 mhz/ 17.92 mhz/ 18.432 mhz/ 24.576 mhz, these scaling factors provide a frequency raster of 16 hz according to the dab specification. by setting the i 2 c bus bit `t', a test signal representing the divided input signal can be monitored at the switching output swc.
U2753B-C preliminary information telefunken semiconductors rev. a1, 30-sep-96 3 (10) main divider the 15-bit main divider is programmable via the i 2 c bus interface. scaling factors from 2048 up to 32767 can be selected. by setting the i 2 c bus bit `t', a test signal repre- senting the divided input signal can be monitored at the switching output swf. when the supply voltage is switched on, both the refer- ence divider and the programmable divider are kept in reset state till a complete scaling factor is written onto the chip. changes in the setting of the programmable divider become active when the corresponding i 2 c bus transmission has been completed. an internal synchronization procedure ensures that such changes do not become active while the charge pump is sourcing or sinking current at its output pin. this behavior allows a smooth tuning of the output frequency without disturbing the controlled vco's frequency spectrum. phase comparator and charge pump the tristate phase detector causes the charge pump to source or to sink current at the output pin pd depending on the phase relation of its input signals which are provided by the reference and the main divider respectively. four different values of this current can be selected by means of the i 2 c bus bits `i50' and `i100'. the charge pump current can be switched off using the i 2 c bus bit `tri'. a change in the setting of the charge pump current becomes active when the corresponding i 2 c bus transmission is completed. as described for the setting of the scaling factor of the programmable divider, an inter- nal synchronization procedure ensures that such changes do not become active while the charge pump is sourcing or sinking current at its output pin. this behavior allows a change in the charge pump current without disturbing the controlled vco's frequency spectrum. a high gain amplifier (output pin: vd) which is implemented in order to construct a loop filter as shown in the application circuit can be switched off by means of the i 2 c bus bit `os'. an internal lock detector checks if the phase difference of the input signals of the phase detector is smaller than approximately 250 ns in seven subsequent comparisons. if phase lock is detected, the open collector output pin plck is set `h' (logical value). it should be noted that the output current of this pin must be limited by external circuitry as it is not limited internally. if the i 2 c bus bit `tri' is set `h' the lock detector function is deactivated and the logical value of the plck output is undefined. switching outputs six switching outputs controlled by the i 2 c bus bits `swc', `swd', `swe', `swf', `swg', `swh' can be used for any switching task on the fronted board. the currents of these outputs are not limited internally. they have to be limited by external circuitry. frequency doubler an internal frequency doubler provides a signal at twice the frequency of the reference signal appearing at the input pins ref and nref. if the i 2 c bus bit `ofd' = `h' the current of its open collector outputs fdo and nfdo is doubled. the frequency doubler function can be switched off by means of the i 2 c bus bit `ofd'. the output signal of the frequency doubler is intended to be used in order to construct an lo signal for the if circuit u2759b in a tuner module. i 2 c bus interface / control various functions can be controlled by a microprocessor- via its i 2 c bus interface these functions are described in the following section `i 2 c bus instruction codes' and `i 2 c bus functions'. by means of the adr pin four different i 2 c bus addresses can be selected as described in the sec- tion `electrical characteristics'. i 2 c bus instruction codes description msb lsb address byte 1 1 0 0 0 as1 as2 0 divider byte 1 0 rd1 rd2 x x n 14 n 13 n 12 divider byte 2 x x n 11 n 10 n 9 n 8 n 7 n 6 divider byte 3 x x n 5 n 4 n 3 n 2 n 1 n 0 control byte 1 1 x 0 os t tri i100 i50 control byte 2 ofd 2ifd swc swd swe swf swg swh control byte 3 x 0 0 0 0 0 0 0
U2753B-C telefunken semiconductors rev. a1, 30-sep-96 preliminary information 4 (10) i 2 c bus function as1, as2 define the i 2 c bus address rd1, rd2 define the scaling factor of the refernce divider: rd1 rd2 scaling factor 0 0 1120 1 0 1152 0 1 1024 1 1 1536 n j scaling factor (sf) of programmable divider sf = sum (n j 2 j ) os os = `h' switches off tuning output t for t= `h' reference signals describing the output frequencies of refernce divider and programmable divider are monitored at swf (main divider) and swc (reference divider) tri tri = `h' switches off charge pump i50, i100 define the charge pump current: i50 i100 charge pump current (nominal) / a `l' `l' 50 `h' `l' 102 `l' `h' 151 `h' `h' 203 ofd ofd = `h' switches off frequency 2ifd 2ifd = `h' doubles the frequency doubler output current swa swa = `h' switches on output current i 2 c bus data transfer format: start - adr - ack - - stop the consists of a sequence of divider bytes and control bytes each followed by ack. divider byte i must be followed by divider byte i + 1 (control byte 1 if i = 3) or the instruction set must be finished. control bytes have to be handled accordingly. examples: start - adr - ack - db1 - ack - db2 - ack - db3 - ack - cb1 - ack - cb2 - ack - cb3 - ack - stop start - adr - ack - cb1 - adk - cb2 - ack - stop however: start - adr - ack - db1 - ack - cb1 - ack - stop is not allowed. description: start start condition stop stop condition ack acknowledge adr address byte dbi divider byte i (i = 1, 2, 3) cbi control byte i (i = 1, 2, 3)
U2753B-C preliminary information telefunken semiconductors rev. a1, 30-sep-96 5 (10) i 2 c bus timing the values of the drawn periods in figure 3, are specified in the section `electrical characteristics'. a typical pulse diagram is shown in figure 4. please note: due to the i 2 c bus specification, the msb of a byte is transmitted first, the lsb last. stop start hddat low r hdsta f high sudat stop start susta hdstat sustp tt t tt t tt t t buf t sda scl 9612016 figure 3. typical pulse diagram start address byte ack divider byte 1 divider byte 2 divider byte 3 control byte 2 control byte 1 stop ack ack ack ack ack sda scl sda scl 9612015 figure 4.
U2753B-C telefunken semiconductors rev. a1, 30-sep-96 preliminary information 6 (10) absolute maximum ratings parameter symbol conditions value unit supply voltage vs 0.3 to 5.5 v rf input voltage (ac) rf, nrf 1 v pp reference input voltage (ac) ref, nref 1 v pp i 2 c bus input/ output voltage scl sda 0.3 to v s v sda output current sda 5 ma address select voltage adr 0.3 to v s v switch output current swa open collector 4 ma switch output voltage swa open collector 0.3 to 5.5 v plck output current plck open collector 0.5 ma plck output voltage plck open collector 0.3 to 5.5 v frequency doubler output voltage fdo, nfdo open collector v s 1 to 5.5 v ambient temperature range t amb 40 to 85 c junction temperature t j 125 c storage temperature t stg 40 to 125 c thermal resistance parameter symbol conditions value unit junction ambient r thja sso20 140 k/w electrical characteristics test conditions: v s = 5 v, t amb = 27 c, unless otherwise specified parameters test conditions / pins symbol min. typ. max. unit supply voltage v s 4.5 5 5.5 v supply current v s sw a = `l', plck = `l', tri = `l', os = `l', i50 = `h', i100 = `h', ofd = `l', 2ifd = `l' i s 12.0 15.1 18.1 ma scaling factor of programmable divider sf 2048 32767 scaling factor of reference divider rd1 = `l', rd2 = `l' rd1 = `h', rd2 = `l' rd1 = `l', rd2 = `h' rd1 = `h', rd2 = `h' sf ref 1120 1152 1024 1536 tuning step 17.920 mhz/ 18.432 mhz/ 16.384 mhz/ 24.576 mhz ref. frequency f rast 16 khz
U2753B-C preliminary information telefunken semiconductors rev. a1, 30-sep-96 7 (10) unit max. typ. min. symbol test conditions / pins parameters rf input, rf, nrf input frequency range v s = 4.5 v, t amb = 20 c 70 500 mhz input sensitivity v rfs 10 20 mv rms max. input signal v rfmax 300 mv rms input impedance differential z rf 200 vswr vswr rf 2 ref input, ref, nref input frequency range v s = 4.5 v, t amb = 20 c f ref 5 17.92 18.432 30 mhz input sensitivity v refs 10 50 mv rms max. input signal v refmax 300 mv rms input impedance single ended z ref 2.7 2.5 k pf phase detector, pd charge pump i100 = `h', i150 = `h' i100 = `h', i50 = `l' i100 = `l', i50 = `h' i100 = `l', i50 = `l' tri = `h' i pd4 i pd3 i pd2 i pd1 i pd, tri 160 120 80 40 203 151 102 50 240 180 120 60 100 a a a a na phase noise i100 = `h', i50 = `h' l pd 155 dbc/hz lock indication, plck leakage current v plck = 5.5 v i plck, l 10 a saturation voltage iplck = 0.5 ma v plck, s at 0.5 v frequency doubler, fdo, nfdo output current v fdo = v s v nfdo = v s 2ifd = `l' i fdol , i nfdol 0.4 0.5 0.6 ma pp v fdo = v s v nfdo = v s 2ifd = `h' i fdoh i nfdoh 0.8 1.0 1.2 ma pp minimum output voltage v s = 5 v v fdo v nfdo 4 v switches, swa leakage current v swa = 5.5 v i sw, l 10 a saturation voltage i swa = 4 ma v sw , sat 0.5 v address selection, adr as1 = 0, as2 = 0 0 0.1 v s as1 = 0, as2 = 1 open as1 = 1, as2 = 0 0.4 v s 0.6 v s as1 = 1, as2 = 1 0.9 v s v s i 2 c bus, scl, sda input voltage, scl/sda `high' `low' v h v l 3 5.5 1.5 v v output voltage sda (open collector) i sda = 2 ma sda = `l' 0.4 v scl clock frequency f scl 0.1 100 khz rise time (scl, sda) t r 1 s fall time (scl, sda) t f 300 ns
U2753B-C telefunken semiconductors rev. a1, 30-sep-96 preliminary information 8 (10) unit max. typ. min. symbol test conditions / pins parameters time before new transmis- sion can be started t buf 4.7 s scl `h' perion t high 4 s scl `l' t low 4.7 s hold time start t hdsta 4 s set up time start t susta 4.7 s set up time stop t sustp 4.7 s fhold time data t hddat 0 s set up time data t sudat 250 ns application circuit bc846b +8.5 v/ +17 v c sda scl 22k +5v address select voltage ref. osc. vs +8.5v band switches tuning voltage vco signal 22k 22k 39n 180n vs u2759b u2750b/ u2309b U2753B-C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 1n 1n 1n 1n 1n 27p (1%) 47nh (5%) 1n 47nh (5%) 180p (1%) l1 l2 l1, l2 : ll1608f47nj (toko) (18p) for f = 36mhz res vs 15p (5%) 600ens9272y (toko) alternative load circuit: 9612018 figure 5.
U2753B-C preliminary information telefunken semiconductors rev. a1, 30-sep-96 9 (10) package sso20 dimensions in mm 0.25+0.05 0.65 6.50+0.1 1.375+0.125 0.15+0.05 4.40+0.1 6.45+0.1 0.05min pin 1 9612017
U2753B-C telefunken semiconductors rev. a1, 30-sep-96 preliminary information 10 (10) ozone depleting substances policy statement it is the policy of temic telefunken microelectronic gmbh to 1. meet all present and future national and international statutory requirements. 2. regularly and continuously improve the performance of our products, processes, distribution and operating systems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment. it is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances ( odss). the montreal protocol ( 1987) and its london amendments ( 1990) intend to severely restrict the use of odss and forbid their use within the next ten years. various national and international initiatives are pressing for an earlier ban on these substances. temic telefunken microelectronic gmbh semiconductor division has been able to use its policy of continuous improvements to eliminate the use of odss listed in the following documents. 1. annex a, b and list of transitional substances of the montreal protocol and the london amendments respectively 2 . class i and ii ozone depleting substances in the clean air act amendments of 1990 by the environmental protection agency ( epa ) in the usa 3. council decision 88/540/eec and 91/690/eec annex a, b and c ( transitional substances ) respectively. temic can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances. we reserve the right to make changes to improve technical design and may do so without further notice . parameters can vary in different applications. all operating parameters must be validated for each customer application by the customer. should the buyer use temic products for any unintended or unauthorized application, the buyer shall indemnify temic against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. temic telefunken microelectronic gmbh, p.o.b. 3535, d-74025 heilbronn, germany telephone: 49 ( 0 ) 7131 67 2831, fax number: 49 ( 0 ) 7131 67 2423
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